1. Field of the Invention
This invention relates generally to a sample and hold circuit for sampling an analog signal, and more particularly to a sample and hold circuit which employs a non-monotonic digital-to-analog converter.
2. Description of the Prior Art
A set-up circuit, or sample and hold circuit, is used primarily for storing the voltage of an analog signal at a specific moment of time. Prior art sample and hold circuits typically employ a switch connected to the analog signal which is to be sampled and a capacitor for temporarily storing the voltage of the analog signal. For example, see the sample and hold circuit described by Millman and Halkias, Integrated Electronics: Analog and Digital Circuits and Systems, McGraw Hill Book Company, 1972, page 570-571. However, capacitive storage type set-up circuits often are subject to "droop" which causes the stored voltage to decrease over time. If the sampled voltage must be retained for several hours, then specially designed capacitors and buffer circuitry must be used in order to avoid this "droop" effect, and system cost is correspondingly increased.
Digital techniques are known for representing an analog signal in digital form. However, if the digital representation is to be reconverted into analog form for subsequent use by other circuitry, a digital-to-analog converter is required. However, most digital-to-analog converters which have been adapted for fabrication as a monolithic integrated circuit require a relatively large die area. This is particularly true when the desired accuracy of the system requires that the digital representation include a large number of bits of information in order to accurately reproduce an analog signal. For example, an 8-bit digital-to-analog (D/A) converter typically includes a least significant current corresponding to the 2.sup.0 bit position and a most significant current corresponding to the 2.sup.7 bit position. In this case, the most significant current ideally must be 128 times as large as the least significant current. In order to accurately maintain the desired 128 to 1 ratio, an integrated circuit must typically employ either resistors having large widths or many smaller width resistors arranged in parallel. In either case, large amounts of integrated circuit die area are required in order to achieve accurate digital-to-analog conversion.
In a sample and hold circuit of the type which embodies the present invention, digital counter is pulsed periodically so as to increment the digital count. The digital count is converted to an analog output voltage by a D/A converter circuit, and the analog output voltage is then compared to the analog voltage to be sampled. When the comparison indicates that the analog output voltage has become equal to or has exceeded the analog voltage to be sampled, the counter stops incrementing.
If the sampled analog signal represents the speed of a system to be controlled, then it is important that the analog output voltage provided by the D/A converter when the counter stops incrementing not be greatly in excess of the analog voltage to be sampled. For example, if the analog voltage to be sampled is derived from a tachometer of an automobile going 55 miles per hour, it would not be permissible to generate an analog output voltage corresponding to 60 miles per hour. Since prior art D/A converters must be very accurate to prevent such errors and would therefore require large die areas resulting in higher chip costs, a sample and hold circuit employing digital techniques to store an analog voltage would not appear to be cost effective where the goal is a low cost system such as a consumer oriented integrated circuit for automotive speed control applications. Yet, the present invention utilizes a D/A converter having high circuit density but which prevents the analog output signal generated by the D/A converter from being significantly in excess of the sampled analog signal.